SRAM Chip Sync Single 1.8V 72M-Bit 2M x 36 0.45ns 165-Pin FBGA

The CY7C1520V18 is a 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 36-bit words in the case of CY7C1520V18 sequentially into or out of the device.

• 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
• 300 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V-VDD)
• Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both Pb-free and non Pb-free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement