SRAM Chip Sync Single 1.8V 18M-Bit 1M x 18 0.45ns 165-Pin FBGA

The CY7C1392JV18, CY7C1992JV18, CY7C1393JV18, and CY7C1394JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C or C is not provided. Each address location is associated with two 8-bit words in the case of CY7C1392JV18, two 9-bit words in the case of CY7C1992JV18, two 18-bit words in the case of CY7C1393JV18, and two 36-bit words in the case of CY7C1394JV18 that burst sequentially into or out of the device.

• 18- Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
• 300 MHz Clock for High Bandwidth
• 2-word Burst for reducing Address Bus Frequency
• Double Data Rate (DDR) Interfaces (data transferred at 600 MHz) at 300 MHz
• Two Input Clocks (K and K) for Precise DDR Timing
  • SRAM uses rising edges only
• Two Input Clocks for Output Data (C and C) to Minimize Clock Skew and Flight Time mismatches
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
• Synchronous Internally Self-timed Writes
• DDR-II operates with 1.5 cycle Read Latency when the DLL is enabled
• Operates similar to a DDR-I Device with one Cycle Read Latency in DLL Off Mode
• 1.8V Core Power Supply with HSTL Inputs and Outputs
• Variable Drive HSTL Output Buffers
• Expanded HSTL Output Voltage (1.4V-VDD)
• Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)
• Offered in both Pb-free and non Pb-free packages
• JTAG 1149.1 compatible Test Access Port
• Delay Lock Loop (DLL) for Accurate Data Placement