SRAM Chip Sync Quad 3.3V 72M-Bit 2M x 36 5.5ns/2.3ns 100-Pin TQFP Tray
SRAM Chip Sync Quad 3.3V 72M-Bit 2M x 36 5.5ns/2.3ns 100-Pin TQFP Tray
- FT pin for user-configurable flow through or pipeline operation
- Dual Cycle Deselect (DCD) operation
- 1.8 V or 2.5 V core power supply
- 1.8 V or 2.5 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 100-lead TQFP package
- RoHS-compliant 100-lead TQFP package available
Caractéristiques
| Brand | GSI Technology |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 2 MWords |
| Density | 72 Mbit |
| Operating temperature | -40 to 85 °C |
| Pin Count | 100 |
| Number Of Ports | 4 |
| Mounting | Surface Mount |
| Address B | 21 Bit |
| Number Of | 36 Bit |
| Number Of | 36 Bit |
| Maximum O | 320@Flow-Through|440@Pipelined mA |
| Product description | 20 x 14 x 1.4 mm |
| Maximum R | 5.5@Flow-Through|2.3@Pipelined ns |
| Supplier | TQFP |
| Typical O | 3.3000 V |
| ECCN | 3A991.B.2.B |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Country of origin | Taiwan |
| Screening Level | Industrial |
| Minimum O | 3 V |
| Maximum O | 3.6 V |
| Maximum C | 181.8@Flow-Through|300@Pipelined MHz |
| Data Rate | SDR |
| Architecture | Flow-Through|Pipelined |
| Lead Finish | Matte Tin |
| Max Proce | 260 |
| Msl Level | 3 |
SKU: GS8640E36GT-300I