SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 12ns/4.5ns 100-Pin TQFP Tray

The GS84036A is a 4,718,592-bit (4,194,304-bit forx32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originallydeveloped for Level 2 Cache applications supporting highperformance CPUs, the device now finds application insynchronous SRAM applications ranging from DSP main storeto networking chip set support. The GS84018/32/36A isavailable in a JEDEC standard 100-lead TQFP or 119-BumpBGA package.

• FT\ pin for user-configurable flow through or pipelined operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO\ pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write and/or Global Write operation
• Common data inputs and data outputs
• Clock control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-bump BGA package (NRND)
• RoHS-compliant 100-lead TQFP and 119-bump BGA packages