SRAM Chip Sync Quad 2.5V/3.3V 36M-Bit 1M x 36 7ns/3.5ns 100-Pin TQFP Tray
SRAM Chip Sync Quad 2.5V/3.3V 36M-Bit 1M x 36 7ns/3.5ns 100-Pin TQFP Tray
- FT pin for user-configurable flow through or pipeline operation
- Dual Cycle Deselect (DCD) operation
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 100-lead TQFP package
- Pb-Free 100-lead TQFP package available
Caractéristiques
| Brand | GSI Technology |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 1 MWords |
| Density | 36 Mbit |
| Operating temperature | 0 to 70 °C |
| Pin Count | 100 |
| Number Of Ports | 4 |
| Mounting | Surface Mount |
| Address B | 20 Bit |
| Number Of | 36 Bit |
| Number Of | 36 Bit |
| Maximum O | 180@Flow-Through|225@Pipelined mA |
| Product description | 20 x 14 x 1.4 mm |
| Maximum R | 7@Flow-Through|3.5@Pipelined ns |
| Supplier | TQFP |
| Typical O | 2.5, 3.3 V |
| ECCN | 3A991.B.2.B |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Screening Level | Commercial |
| Minimum O | 2.3, 3 V |
| Maximum O | 2.7, 3.6 V |
| Maximum C | 142.8@Flow-Through|166@Pipelined MHz |
| Data Rate | SDR |
| Architecture | Flow-Through|Pipelined |
| Lead Finish | Matte Tin |
| Max Proce | 260 |
| Msl Level | 3 |
SKU: GS8320E36GT-166