SRAM Chip Sync Quad 2.5V/3.3V 36M-Bit 1M x 36 4.5ns/2.5ns 165-Pin FBGA
SRAM Chip Sync Quad 2.5V/3.3V 36M-Bit 1M x 36 4.5ns/2.5ns 165-Pin FBGA
- FT pin for user-configurable flow through or pipeline operation
- Dual Cycle Deselect (DCD) operation
- IEEE 1149.1 JTAG-compatible Boundary Scan
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 165-bump BGA package
- Rosh-compliant 165-bump BGA package available
- 2nd Generation, Green 13 mm x 15 mm, 165 FPBGA
- 333 MHz Frequency
Caractéristiques
| Brand | GSI Technology |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 1 MWords |
| Density | 36 Mbit |
| Operating temperature | 0 to 85 °C |
| Pin Count | 165 |
| Number Of Ports | 4 |
| Mounting | Surface Mount |
| Address B | 20 Bit |
| Number Of | 36 Bit |
| Number Of | 36 Bit |
| Maximum O | 300@Flow-Through|390@Pipelined mA |
| Product description | 15 x 13 x 0.94 mm |
| Maximum R | 4.5@Flow-Through|2.5@Pipelined ns |
| Supplier | FBGA |
| Typical O | 2.5, 3.3 V |
| ECCN | 3A991.B.2.B |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Country of origin | Taiwan |
| Screening Level | Commercial |
| Minimum O | 2.3, 3 V |
| Maximum O | 2.7, 3.6 V |
| Maximum C | 222@Flow-Through|333@Pipelined MHz |
| Data Rate | SDR |
| Architecture | Flow-Through|Pipelined |
| Msl Level | 3 |
SKU: GS8321E36AGD-333