SRAM Chip Sync Dual 1.8V 18M-Bit 1M x 18 0.45ns 165-Pin FBGA

The CY7C1312CV18 is 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 18-bit words (CY7C1312CV18), or 36-bit words (CY7C1314CV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks, memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 250 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz
• Two input clocks for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data to minimize clock skew and flight time mismatches
• Echo clocks simplify data capture in high-speed systems
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• QDR™-II operates with 1.5 cycle read latency when the Delay Lock Loop (DLL) is enabled
• Operates as a QDR-I device with 1 cycle read latency in DLL off mode
• Available in x 8, x 9, x 18, and x 36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8 (±0.1V); IO VDDQ = 1.4V to VDD
• Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
• Offered in both Pb-free and non Pb-free packages
• Variable drive HSTL output buffers
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement