SRAM Chip Async Single 2.5V/3.3V 4M-Bit 256K x 16 55ns 48-Pin VFBGA

The CY62147DV30 is a high-performance CMOS static RAM organized as 256K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The devices also have an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected or when CE is LOW and both BLE and BHE are HIGH. The input/output pins are placed in a high-impedance state when: deselected, outputs are disabled, BHE and BLE are disabled, or during a write operation. Writing to the device is accomplished by taking Chip Enable and Write Enable inputs LOW. If Byte Low Enable is LOW, then data from I/O pins, is written into the location specified on the address pins. If Byte High Enable is LOW, then data from I/O pins is written into the location specified on the address pins. Reading from the device is accomplished by taking Chip Enable and Output Enable LOW while forcing the Write Enable HIGH. If Byte Low Enable is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.

• Very high speed: 45 ns
• Wide voltage range: 2.20V-3.60V
• Pin-compatible with CY62147CV25, CY62147CV30, and CY62147CV33
• Ultra-low active power
  • Typical active current: 1.5 mA @ f = 1 MHz
  • Typical active current: 8 mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE/ and OE/, and features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered 48-ball BGA and 44-pin TSOPII
• Also available in Lead-Free packages
• Byte power-down feature