SRAM Chip Async Dual 5V 64K-Bit 64K x 1 25ns 24-Pin SOJ

The CY7C187 is a high-performance CMOS static RAM organized as 65,536 words x 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and tri-state drivers. The CY7C187 has an automatic power-down feature, reducing the power consumption by 56% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Enable (CE) LOW, while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pin will appear on the data output (DOUT) pin. The output pin stays in high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. The CY7C187 utilizes a die coat to insure alpha immunity.

• High speed
  • 15 ns
• CMOS for optimum speed/power
• Low active power
  • 495 mW
• Low standby power
  • 110 mW
• TTL compatible inputs and outputs
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 22-pin (300-Mil) Molded DIP and 24-pin (300-Mil) Molded SOJ