SRAM Chip Async Dual 5V 32K-Bit 4K x 8 15ns 52-Pin PLCC

The CY7C1357C is a 3.3 V, 256 K × 36 / 512 K × 18 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1357C is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use
• Registered inputs for flow-through operation
• Byte write capability
• 3.3 V / 2.5 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 6.5 ns (for 133-MHz device)
• Clock enable (CE/ and OE/?) pin to enable clock and suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• Available in JEDEC-standard and Pb-free 100-pin TQFP and 165-ball FBGA package
• Three chip enables for simple depth expansion.
• Automatic power-down feature available using ZZ mode or CE deselect
• IEEE 1149.1 JTAG-compatible boundary scan
• Burst capability - linear or interleaved burst order
• Low standby power