SRAM Chip Async Dual 5V 1M-Bit 1M x 1 15ns 28-Pin SOJ

The CY7C1007BN is high-performance CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable and three-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when deselected. Writing to the devices is accomplished by taking Chip Enable and Write Enable inputs LOW. Data on the input pin is written into the memory location specified on the address pins. Reading from the devices is accomplished by taking Chip Enable LOW while Write Enable remains HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the data output pin. The output pin is placed in a high-impedance state when the device is deselected or during a write operation. The CY7C107BN is available in a standard 400-mil-wide SOJ; the CY7C1007BN is available in a standard 300-mil-wide SOJ

• High speed
  • tAA = 15 ns
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs