Registered Bus Exchanger 1-Element 56-Pin SSOP Tube

This 9-bit, 4-port universal bus exchanger is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16409 allows synchronous data exchange between four different buses. Data flow is controlled by the select (SEL0-SEL4) inputs. A data-flow state is stored on the rising edge of the clock (CLK) input if the select-enable (SELEN\) input is low. Once a data-flow state has been established, data is stored in the flip-flop on the rising edge of CLK if SELEN\ is high. The data-flow control logic is designed to allow glitch-free data transmission. When preset (PRE\) transitions high, the outputs are disabled immediately, without waiting for a clock pulse. To leave the high-impedance state, both PRE\ and SELEN\ must be low and a clock pulse must be applied. To ensure the high-impedance state during power up or power down, PRE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

Member of the Texas Instruments Widebus+™ Family

UBE™ (Universal Bus Exchanger) Allows Synchronous Data Exchange

Operates From 1.65-V to 3.6-V

Max t_pd of 5.1 ns at 3.3-V

±24 mA Output Drive at 3.3-V

Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

Latch-Up Performance Exceeds 250 mA Per JESD 17

ESD Performance Tested Per JESD 22

• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)