Ethernet Switch 3-Port 10Mbps/100Mbps 72-Pin QFN EP

The LAN9303Mi is a full featured, 3 port 10/100 managed Ethernet switch designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9303Mi combines all the functions of a 10/100 switch system, including the Switch Fabric, packet buffers, Buffer Manager, Media Access Controllers (MACs), PHY transceivers, and serial management. The LAN9303Mi complies with the IEEE 802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol specification and 802.1D/802.1Q network management protocol specifications, enabling compatibility with industry standard Ethernet and Fast Ethernet applications.

• Ethernet Switch Fabric
  • 32K buffer RAM
  • 512 entry forwarding table
  • Port based IEEE 802.1Q VLAN support (16 groups) – Programmable IEEE 802.1Q tag insertion/removal
  • IEEE 802.1D spanning tree protocol support
  • 4 separate transmit queues available per port
  • Fixed or weighted egress priority servicing
  • QoS/CoS Packet prioritization – Input priority determined by VLAN tag, DA lookup,
• TOS, DIFFSERV or port default value – Programmable Traffic Class map based on input priority on per port basis – Remapping of 802.1Q priority field on per port basis – Programmable rate limiting at the ingress with coloring and random early discard, per port / priority – Programmable rate limiting at the egress with leaky bucket algorithm, per port / priority
  • IGMP v1/v2/v3 monitoring for Multicast packet filtering
  • Programmable broadcast storm protection with global % control and enable per port
  • Programmable buffer usage limits
  • Dynamic queues on internal memory
  • Programmable filter by MAC address
• Switch Management
  • Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any port or port pair
  • Fully compliant statistics (MIB) gathering counters
  • Control registers configurable on-the-fly
• Ports
  • Port 0 - MII MAC, MII PHY, RMII PHY modes
  • Port 1 - MII MAC, MII PHY, RMII PHY mode options
  • 2 internal 10/100 PHYs with HP Auto-MDIX support
  • 200Mbps Turbo MII (PHY or MAC mode)
  • Fully compliant with IEEE 802.3 standards
  • 10BASE-T and 100BASE-TX support
  • Full and half duplex support
  • Full duplex flow control
  • Backpressure (forced collision) half duplex flow control
  • Automatic flow control based on programmable levels
  • Automatic 32-bit CRC generation and checking
  • 2K Jumbo packet support
  • Programmable interframe gap, flow control pause value
  • Full transmit/receive statistics
  • Full LED support per port
  • Auto-negotiation
  • Automatic polarity correction
  • Automatic MDI/MDI-X
  • Loop-back mode
• Serial Management
  • I2C (slave) access to all internal registers
  • MIIM (MDIO) access to PHY related registers
  • SMI (extended MIIM) access to all internal registers
• Other Features
  • General Purpose Timer
  • I2C Serial EEPROM interface
  • Programmable GPIOs/LEDs
• Single 3.3V power supply
• ESD Protection Levels
  • ±8kV HBM without External Protection Devices
  • ±8kV contact mode (IEC61000-4-2)
  • ±15kV air-gap discharge mode (IEC61000-4-2)
• Latch-up exceeds ±150mA per EIA/JESD 78
• 72-pin QFN (10x10 mm) Lead-Free RoHS Compliant Package
• Available in Commercial & Industrial Temp. Ranges