Ethernet Switch 3-Port 10Mbps/100Mbps 100-Pin LFBGA Tray

The KSZ8893MBL, a highly integrated layer 2 managed switch, is designed for low port count, cost-sensitive 10/100 Mbps switch systems. It offers an extensive feature set that includes rate limiting, tag/port-based VLAN, QoS priority, management, management information base (MIB) counters, RMII/MII/SNI, and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications.The KSZ8893MBL contains two 10/100 transceivers with patented mixed-signal low-power technology, three media access control (MAC) units, a high-speed non--blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory.Both PHY units support 10BASE-T and 100BASETX. In addition, one PHY unit supports 100BASE-FX. The KSZ8893MBL comes in a lead-free package, and is also available in industrial temperature-grade KS8893MQLI/MBLI and Automotive-grade KSZ8893 MQL AM.

• Proven Integrated 3-Port 10/100 Ethernet Switch
  • 3rd generation switch with three MACs and two PHYs fully compliant with IEEE 802.3u standard
  • non--blocking switch fabric assures fast packet delivery by utilizing an 1K MAC address lookup table and a store-and-forward architecture
  • Full duplex IEEE 802.3x flow control (PAUSE) with force mode option
  • Half-duplex back pressure flow control
  • HP Auto MDI-X for reliable detection of and correction for straight-through and crossover cables with disable and enable option
  • Micrel LinkMD™ TDR-based cable diagnostics permit identification of faulty copper cabling
  • 100BASE-FX support on port 1
  • MII interface supports both MAC mode and PHY mode
  • RMII interface support with external 50MHz system clock
  • 7-wire serial network interface (SNI) support for legacy MAC
  • Comprehensive LED Indicator support for link, activity, full/half duplex and 10/100 speed
• Comprehensive Configuration Register Access
  • Serial management interface (SMI) to all internal registers
  • MII management (MIIM) interface to PHY registers
  • SPI and I²C Interface to all internal registers
  • I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode
  • Control registers configurable on the fly (port-priority, 802.1p/d/q, AN…)
• QoS/CoS Packet Prioritization Support
  • Per port, 802.1p and DiffServ-based
  • Re-mapping of 802.1p priority field per port basis
  • Four priority levels
• Low Latency Support
  • Repeater mode
• Switch Monitoring Features
  • Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII
  • MIB counters for fully compliant statistics gathering, 34 MIB counters per port
  • Loopback modes for remote diagnostic of failure
• Low Power Dissipation:
  • Full-chip hardware power-down (register configuration not saved)
  • Per port based software power-save on PHY (idle link detection, register configuration preserved)
  • Voltages: Single power supply: 3.3V
• Industrial Temperature Range: -40°C to +85°C