Switch Fabric 512 x 512 3.3V 144-Pin L-BGA Tray

The device has 16 ST-BUS inputs (STi0-15) and 16 ST-BUS outputs (STo0-15). It is a non-blocking digital switch with 512 64 kbps channels and performs rate conversion between the ST-BUS inputs and ST-BUS outputs. The ST-BUS inputs accept serial input data streams with the data rate of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps on a per-stream basis. The ST-BUS outputs deliver serial output data streams with the data rate of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps on a per-stream basis. The device also provides 16 high impedance control outputs (STOHZ 0-15) to support the use of external high impedance control buffers. The ZL50011GDG2 has features that are programmable on a per-stream or per-channel basis including message mode, input bit delay, output bit advancement, constant throughput delay and high impedance output control. The on-chip DPLL meets Telcordia GR-1244-CORE stratum 4 specifications (Stratum 4). It accepts a dedicated timing reference input at either 8 kHz, 1.544 MHz or 2.048 MHz. Alternatively, the reference can be replaced by an internal 8 kHz signal derived from the ST-BUS input frame boundary. The DPLL provides reference monitor, jitter attenuation and free run functions. It can be used as a system’s ST-BUS timing source which is synchronized to the network. The DPLL can also be bypassed so that the device operates under system timing.

• Package: 144 Ball LBGA
• 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation
• Rate conversion between the ST-BUS inputs and ST-BUS outputs
• Integrated Digital Phase-Locked Loop (DPLL) meets Telcordia GR-1244-CORE Stratum 4 specifications
• DPLL provides reference monitor, jitter attenuation and free run functions
• Per-stream ST-BUS input with data rate selection of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps
• Per-stream ST-BUS output with data rate selection of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps; the output data rate can be different than the input data rate
• Per-stream high impedance control output for every ST-BUS output with fractional bit advancement
• Per-stream input channel and input bit delay programming with fractional bit delay
• Per-stream output channel and output bit delay programming with fractional bit advancement
• Multiple frame pulse outputs and reference clock outputs
• Per-channel constant throughput delay
• Per-channel high impedance output control
• Per-channel message mode
• Per-channel Pseudo Random Bit Sequence (PRBS) pattern generation and bit error detection
• Control interface compatible to Motorola nonmultiplexed CPUs
• Connection memory block programming capability
• IEEE-1149.1 (JTAG) test port
• 3.3 V I/O with 5 V tolerant input