SRAM Chip Sync Single 2.5V 9M-Bit 256K x 36 0.7ns 165-Pin FBGA

The CY7C1308DV25C is a 2.5V Synchronous Pipelined SRAM equipped with DDR I (Double Data Rate) architecture. The DDR I architecture consists of an SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/?are not provided. Every Read or Write operation is associated with four words that burst sequentially into or out of the device. The burst counter takes in the least two significant bits of the external address and bursts four 36-bit words. Depth expansion is accomplished with Port Selects for each port. Port Selects allow each port to operate independently. Asynchronous inputs include impedance match (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks (C/?) are also provided for maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or ? input clocks. Writes are conducted with on-chip synchronous self timed write circuitry.

• 9 Mbit Density (256 Kbit x 36)
• 250 MHz Clock for High Bandwidth
• 4-Word Burst to Reduce Address Bus Frequency
• Double Data Rate (DDR) Interfaces (data transferred at 500 MHz at 250 MHz)
• Two Input Clocks for Precise DDR Timing-SRAM uses rising edges only
• Two Input Clocks Account for Clock Skew and Flight Time Mismatching
• Separate Port Selects for Depth Expansion
• Synchronous Internally Self-timed Writes
• 2.5V Core Power Supply with HSTL Inputs and Outputs
• Variable Drive HSTL Output Buffers
• Expanded HSTL Output Voltage (1.4V to 1.9V)
• 13 x 15 x 1.4 mm 1.0 mm pitch fBGA package, 165 ball (11 x 15 matrix)
• JTAG 1149.1 Compatible Test Access Port