SRAM Chip Sync Single 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin FBGA

The CY7C1320CV18 is 1.8 V synchronous pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K. Read data is driven on the rising edges of C and ? if provided, or on the rising edge of K if C/?are not provided. For CY7C1318CV18 and CY7C1320CV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words of two 36-bit words (in the case of CY7C1320CV18) sequentially into or out of the device. Asynchronous inputs include an output impedance matching input . Synchronous data outputs are tightly matched to the two output echo clocks, eliminating the need to capture data separately from each individual DDR SRAM in the system design. Output data clocks enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K input clocks. All data outputs pass through output registers controlled by the C or ? input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

• 18-Mbit density (1 M × 18, 512 K × 36)
• 267-MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 534 MHz) at 267 MHz
• Two input clocks for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data to minimize clock skew and flight time mismatches
• Echo clocks simplify data capture in high speed systems
• Synchronous internally self-timed writes
• DDR II operates with 1.5 cycle read latency when delay lock loop (DLL) is enabled
• Operates similar to a DDR I device with one cycle read latency in DLL Off mode
• 1.8 V core power supply with high-speed transceiver logic (HSTL) inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4 V - VDD)
• Available in 165-ball fine pitch ball grid array (FPBGA) package (13 × 15 × 1.4 mm)
• Offered in both Pb-free and non Pb-free packages
• JTAG 1149.1 compatible test access port
• DLL for accurate data placement