SRAM Chip Sync Single 1.3V 144M-Bit 8M x 18 361-Pin FCBGA

The QDR-IV XP (Xtreme Performance) SRAM is a high-performance memory device optimized to maximize the number of random transactions per second by the use of two independent bidirectional data ports. These ports are equipped with DDR interfaces and designated as port A and port B respectively. Accesses to these two data ports are concurrent and independent of each other. Access to each port is through a common address bus running at DDR. The control signals are running at SDR and determine if a read or write should be performed. There are three types of differential clocks: ¦ (CK, CK#) for address and command clocking ¦ (DKA, DKA#, DKB, DKB#) for data input clocking ¦ (QKA, QKA#, QKB, QKB#) for data output clocking Addresses for port A are latched on the rising edge of the input clock (CK), and addresses for port B are latched on the falling edge of the input clock (CK). This QDR-IV XP SRAM is internally partitioned into eight internal banks. Each bank can be accessed once for every clock cycle, enabling the SRAM to operate at high frequencies. The QDR-IV XP SRAM device is offered in a two-word burst option and is available in × 18 and × 36 bus width configurations. For an ×18 bus-width configuration, there are 22 address bits, and for an ×36 bus width configuration, there are 21 address bits respectively. An on-chip ECC circuitry detects and corrects all single-bit memory errors including those induced by soft error events, such as cosmic rays and alpha particles. The resulting SER of these devices is expected to be less than 0.01 FITs/Mb, a four-order-of-magnitude improvement over previous generation SRAMs.

• 144-Mbit density (8 M × 18, 4 M × 36)
• Total Random Transaction Rate[1] of 2132 MT/s
• Maximum operating frequency of 1066 MHz
• Read latency of 8.0 clock cycles and write latency of 5.0 clock cycles
• Eight-bank architecture enables one access per bank per cycle
• Two-word burst on all accesses
• Dual independent bidirectional data ports
  • Double data rate (DDR) data ports
  • Supports concurrent read/write transactions on both ports
• Single address port used to control both data ports
  • DDR address signaling
• Single data rate (SDR) control signaling
• High-speed transceiver logic (HSTL) and stub series terminated logic (SSTL) compatible signaling (JESD8-16A compliant)
  • I/O VDDQ = 1.2 V ± 50 mV or 1.25 V ± 50 mV
• Pseudo open drain (POD) signaling (JESD8-24 compliant)
  • I/O VDDQ = 1.1 V ± 50 mV or 1.2 V ± 50 mV
• Core voltage
  • VDD = 1.3 V ± 40 mV
• On-die termination (ODT)
  • Programmable for clock, address/command, and data inputs
• Internal self-calibration of output impedance through ZQ pin
• Bus inversion to reduce switching noise and power
  • Programmable on/off for address and data
• Address bus parity error protection
• Training sequence for per-bit deskew
• On-chip error correction code (ECC) to reduce soft error rate (SER)
• JTAG 1149.1 test access port (JESD8-26 compliant)
  • 1.3 V LVCMOS signaling
• Available in 361-ball FCBGA Pb-free package (21 × 21 mm)