SRAM Chip Sync Quad 1.8V/2.5V 18M-Bit 512K x 32 5.5ns 100-Pin TQFP Bulk
The GS8160E32DGT is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
- FT pin for user-configurable flow through or pipeline operation
- Dual Cycle Deselect (DCD) operation
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- RoHS-compliant 100-lead TQFP package available
- 1MB product Family
- Green TQFP
Especificaciones
| Brand | GSI Technology |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 512 kWords |
| Density | 18 Mbit |
| Operating temperature | 0 to 70 °C |
| Pin Count | 100 |
| Number Of Ports | 4 |
| Mounting | Surface Mount |
| Address B | 19 Bit |
| Number Of | 32 Bit |
| Number Of | 32 Bit |
| Maximum O | 245 mA |
| Product description | 14 x 20 x 1.4 mm |
| Maximum R | 5.5 ns |
| Supplier | TQFP |
| Typical O | 1.8, 2.5 V |
| ECCN | 3A991.B.2.B |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Country of origin | Taiwan |
| Screening Level | Commercial |
| Minimum O | 1.7, 2.3 V |
| Maximum O | 2, 2.7 V |
| Maximum C | 250 MHz |
| Data Rate | SDR |
| Architecture | Flow-Through|Pipelined |
SKU: GS8160E32DGT-250V