SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 3.5ns 100-Pin TQFP

The CY7C1327G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable , depth-expansion chip enables, burst control inputs (ADSC, ADSP, and ADV), write enables, and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

• Registered inputs and outputs for pipelined operation
• 256 K × 18 common I/O Architecture
• 3.3 V core power supply (VDD)
• 2.5 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 3.5 ns (for 166-MHz device)
• Provide high performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in Pb-free 100-pin TQFP package
• “ZZ” sleep mode option