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SRAM Chip Sync Dual 3.3V 144K-Bit 8K x 18 20ns/9ns 100-Pin TQFP

The CY7C09349AV and CY7C09359AV are high-speed 3.3 V synchronous CMOS 4 K and 8 K × 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time.
  • True dual ported memory cells which allow simultaneous access of the same memory location
  • Two flow-through/pipelined devices
    • 8 K × 18 organization (CY7C09359AV)
  • Three modes
    • Flow-through
    • Pipelined
    • Burst
  • Pipelined output mode on both ports allows fast 67-MHz operation
  • 0.35-micron complementary metal oxide semiconductor (CMOS) for optimum speed/power
  • High-speed clock to data access 9 and 12 ns (max)
  • 3.3 V low operating power
    • Active = 135 mA (typical)
    • Standby = 10 µA (typical)
  • Fully synchronous interface for easier operation
  • Burst counters increment addresses internally
    • Shorten cycle times
    • Minimize bus noise
    • Supported in flow-through and pipelined modes
  • Dual chip enables for easy depth expansion
  • Upper and lower byte controls for bus matching
  • Automatic power-down
  • Available in 100-pin thin quad flat pack (TQFP)

Especificaciones

Brand Rochester Electronics
Datasheet PDF
Timing Type Synchronous
Number Of Words 8 kWords
Density 144 Kb
Operating temperature 0 to 70 °C
Pin Count 100
Number Of Ports 2
Mounting Surface Mount
Address B 13 Bit
Number Of 18 Bit
Number Of 18 Bit
Maximum O 230 mA
Product description 14 x 14 x 1.4 mm
Maximum R 20@Flow-Through|9@Pipelined ns
Supplier TQFP
Typical O 3.3000 V
ECCN EAR99
Schedule B 8542320040
HTSN 8542320041
Country of origin United States
Maximum C 40@Flow-Through|67@Pipelined MHz
Data Rate SDR
Architecture Flow-Through|Pipelined
Lead Finish Matte Tin|Gold
Max Proce 260
Msl Level 3
SKU: CY7C09359AV-9AXC