SRAM Chip Sync Dual 1.8V 72M-Bit 4M x 18 0.45ns 165-Pin FBGA

The GS8672D20BE Sigma Quad-II ECCRAMs are built in compliance with the Sigma Quad-II SRAM pin out standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) ECCRAMs. The GS8672D20BE Sigma Quad-II ECCRAMs are just one element in a family of Low power, Low voltage HSTL I/O ECCRAMs designed to operate at the speeds needed to implement economical High performance networking systems.

• On-Chip ECC with virtually zero SER
• Simultaneous Read and Write Sigma Quad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write Capability
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with 18Mb, 36Mb, and 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available