SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 28-Pin TSOP-I

The CY62256 is a high-performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable and active LOW output enable and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. An active LOW write enable signal controls the writing/reading operation of the memory. When chip enable and write enable inputs are both LOW, data on the eight data input/output pins is written into the memory location addressed by the address present on the address pins. Reading the device is accomplished by selecting the device and enabling the outputs, chip enable and output enable active LOW, while write enable remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable is HIGH.

• Temperature Ranges
  • Commercial: 0°C to 70°C
  • Industrial: -40°C to 85°C
  • Automotive: -40°C to 125°C
• High speed: 55 ns and 70 ns
• Voltage range: 4.5V-5.5V operation
• Low active power (70 ns, LL version, Com’l and Ind’l)
  • 275 mW (max.)
• Low standby power
  • 28 µW (max.)
• Easy memory expansion with CE/ and OE/ and features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow SOIC, 28-lead TSOP-1, 28-lead reverse TSOP-1, and 600-mil 28-lead PDIP packages