SRAM Chip Async Single 3.3V 1M-Bit 64K x 16 15ns 44-Pin TSOP-II T/R

The IS64WV6416BLL is a high-speed, 1,048,576- bit static RAM organized as 65,536 words by 16 bits. It is fabricated using high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12ns (3.3V + 10%) and 15ns (2.5V-3.6V) with low power consumption. When CE\ is HIGH (deselected), the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE\ and OE\. The active LOW Write Enable (WE\) controls both writing and reading of the memory. A data byte allows Upper Byte (UB\) and Lower Byte (LB\) access. The IS61/64WV6416BLL is packaged in the JEDEC standard 44-pin TSOP-II, 44-pin 400-mil SOJ, and 48-pin mini BGA (6mm x 8mm).

• High-speed access time
  • 12 ns: 3.3V + 10%
  • 15 ns: 2.5V-3.6V
• CMOS low power operation
  • 50 mW (typical) operating
  • 25 µW (typical) standby
• TTL compatible interface levels
• Fully static operation: no clock or refresh required
• Three state outputs
• Data control for upper and lower bytes
• Automotive Temperature Available
• Lead-free available