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SRAM Chip Async Single 2.8V/3.3V 4M-Bit 512K x 8 45ns 32-Pin TSOP-II T/R

The IS62WV5128EBLL are high speed, low power, 4M bit SRAMs organized as 512K words by 8 bits. It is fabricated high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1\ is HIGH (deselected) or when CS1\ is low and both LB\ and UB\ are HIGH, the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable(WE\) controls both writing and reading of the memory. A data byte allows Upper Byte (UB\) and Lower Byte (LB\) access. The IS62WV5128EBLL are packaged in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin mini BGA (6mmx8mm).
  • High-speed access time: 35ns, 45ns, 55ns
  • CMOS low power operation
    • Operating Current: 22 mA (max) at 85°C
    • CMOS Standby Current: 3.7uA (typ) at 25°C
  • TTL compatible interface levels
  • Single power supply: 2.2V-3.6V Vdd (IS62/65WV5128EBLL)
  • Three state outputs
  • Industrial and Automotive temperature support
  • Lead-free available

Especificaciones

Brand ISSI
Datasheet PDF
Number Of Words 512 kWords
Density 4 Mbit
Operating temperature -40 to 85 °C
Pin Count 32
Number Of Ports 1
Mounting Surface Mount
Address B 19 Bit
Number Of 8 Bit
Number Of 8 Bit
Maximum O 22 mA
Product description 20.95 x 10.16 x 1
Maximum R 45 ns
Supplier TSOP-II
Typical O 2.8, 3.3 V
ECCN 3A991
Schedule B 8542320040
HTSN 8542320041
Country of origin Taiwan
Screening Level Industrial
Minimum O 2.2 V
Maximum O 3.6 V
Lead Finish Matte Tin
Max Proce 260
Msl Level 3
SKU: IS62WV5128EBLL-45T2LI-TR