SRAM Chip Async Single 2.5V/3.3V 2M-Bit 128K x 16 45ns 44-Pin TSOP-II

The CY62136EV30 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected. The input/output pins are placed in a high impedance state when: deselected, outputs are disabled, both Byte High Enable and Byte Low Enable are disabled, or during a write operation. Writing to the device is accomplished by taking Chip Enable and Write Enable inputs LOW. If Byte Low Enable is LOW, then data from I/O pins , is written into the location specified on the address pins. If Byte High Enable is LOW, then data from I/O pins is written into the location specified on the address pins. Reading from the device is accomplished by taking Chip Enable and Output Enable LOW while forcing the Write Enable HIGH. If Byte Low Enable is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable is LOW, then data from memory appear on I/O8 to I/O15.

• Very high speed: 45 ns
• Wide voltage range: 2.20 V to 3.60 V
• Pin compatible with CY62136CV30
• Ultra low standby power
  • Typical standby current: 1 µA
  • Maximum standby current: 7 µA
• Ultra low active power
  • Typical active current: 2 mA at f = 1 MHz
• Easy memory expansion with CE/ and OE/ and features
• Automatic power down when deselected
• Complementary metal oxide semiconductor (CMOS) for optimum speed/power
• Offered in a Pb-free 48-ball very fine ball grid array (VFBGA) and 44-pin thin small outline package (TSOP II) packages