SRAM Chip Async Single 2.5V/3.3V 1M-Bit 128K x 8 70ns 32-Pin SOIC

The CY62128DV30 is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 HIGH or Chip Enable 2 LOW. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 HIGH or Chip Enable 2 LOW, outputs are disabled, or during a write operation (Chip Enable 1 LOW and Chip Enable 2 HIGH and Write Enable LOW). Writing to the device is accomplished by taking Chip Enable 1 LOW with Chip Enable 2 HIGH and Write Enable LOW. Data on the eight I/O pins is then written into the location specified on the Address pin (A0 through A16). Reading from the device is accomplished by taking Chip Enable 1 LOW with Chip Enable 2 HIGH and Output Enable LOW while forcing the Write Enable HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/Oo through I/O7) are placed in a high-impedance state when the device is deselected, the outputs are disabled or during a write operation.

• Very high speed: 55 and 70 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62128V
• Ultra-low active power
  • Typical active current: 0.85 mA @ f = 1 MHz
  • Typical active current: 5 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE/ and OE1/, CE2, and features
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 32-lead SOIC, 32-lead TSOP and 32-lead Small TSOP, non Pb-free 32-lead Reverse TSOP packages