SRAM Chip Async Dual 5V 16K-Bit 2K x 8 25ns 52-Pin PLCC

The CY7C146 is high-speed CMOS 2K by 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132/ CY7C136 can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the left port and 7FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C146 is available in 52-pin PLCC and PQFP.

• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• 2K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 90 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• BUSY input CY7C146
• INT flag for port-to-port communication (52-pin PLCC/PQFP versions)
• 52-pin PLCC and 52-pin TQFP (CY7C146)
• Pin-compatible and functionally equivalent to IDT7132/IDT7142