NOR Flash Parallel 1.8V 16Mbit 2M/1M x 8bit/16bit 70ns 48-Pin FBGA Tray

The S29AS016J is a 16 Mbit, 1.8 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words with a x8/x16 bus and either top or bottom boot sector architecture. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and erased in-system with the standard system 1.8 volt VCC supply. A 12.0V VPP or 5.0 VCC are not required for program or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access time of 70 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The S29AS016J is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector group protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

• Architectural Advantages
• Single Power Supply Operation
  • Full voltage range: 1.65 to 1.95 volt read and write operations for battery-powered applications
• Manufactured on 110 nm Process Technology
  • Backward compatible with 0.32 µm Am29SL160C device
• Secured Silicon Sector region
  • 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence
  • May be programmed and locked at the factory or by the customer
• Flexible Sector Architecture
  • Eight 8 Kbyte and thirty-one 64 Kbyte sectors (byte mode)
  • Eight 4 Kword, and thirty-one 32 Kword sectors (word mode)
• Sector Group Protection Features
  • A hardware method of locking a sector to prevent any program or erase operations within that sector
  • Sectors can be locked in-system or via programming equipment
  • Temporary Sector Group Unprotect feature allows code changes in previously locked sectors
• Unlock Bypass Program Command
  • Reduces overall programming time when issuing multiple program command sequences
• Top or Bottom Boot Block Configurations Available
• Compatibility with JEDEC standards
  • Pinout and software compatible with single-power supply Flash
  • Superior inadvertent write protection Performance Characteristics
• High Performance
  • Access times as fast as 70 ns
  • Industrial temperature range (-40°C to +85°C)
  • Automotive In-Cabin temperature range (-40°C to +105°C)
  • Word programming time as fast as 6 µs (typical)
• Ultra Low Power Consumption (typical values at 5 MHz)
  • 15 µA Automatic Sleep mode current
  • 8 µA standby mode current
  • 8 mA read current
  • 20 mA program/erase current
• Cycling Endurance: 1,000,000 cycles per sector typical
• Data Retention: 20 years typical Package Options
• 48-ball Fine-Pitch BGA, 8.15 mm x 6.15 mm
• 48-ball Fine-Pitch BGA, 6.0 mm x 4.0 mm
• 48-pin TSOP Software Features
• CFI (Common Flash Interface) Compliant
  • Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
• Erase Suspend/Erase Resume
  • Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
• Data# Polling and Toggle Bits
  • Provides a software method of detecting program or erase operation completion Hardware Features
• Ready/Busy# Pin (RY/BY#)
  • Provides a hardware method of detecting program or erase cycle completion
• Hardware Reset Pin (RESET#)
  • Hardware method to reset the device to reading array data
• WP# input pin
  • Write protect (WP#) function allows protection of two outermost boot sectors (boot sector models only), regardless of sector group protect status