DSP Floating-Point 32-Bit 200MHz 1600MIPS 272-Pin BGA Tray

The TMS320C67x DSPs (including the SM320C6713 and SM320C6713B devices) compose the floating-point DSP generation in the TMS320C6000 DSP platform. The C6713 and C6713B devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. Throughout the remainder of this document, the SM320C6713 and SM320C6713B are referred to as 320C67x or C67x or 13/13B where generic, and where specific, their individual full device part numbers are used or abbreviated as C6713, C6713B, 13, or 13B, and so forth. Operating at 225 MHz, the C6713/13B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS). Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS). The C6713/13B has a rich peripheral set that includes two multichannel audio serial ports (McASPs), two multichannel buffered serial ports (McBSPs), two inter-integrated circuit (I2C) buses, one dedicated general-purpose input/output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASPs has eight serial data pins that can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713/13B has sufficient bandwidth to support all 16 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, and CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock, which verifies that the master clock is within a programmed frequency range. The two I2C ports on the 320C6713/13B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The 320C6713/13B device has two boot modes—from the HPI or from external asynchronous ROM. For more detailed information, see the Bootmode section of this data sheet. The TMS320C67x DSP generation is supported by the TI eXpressDSP set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS kernel.

Highest Performance Floating Point Digital Signal Processors (DSPs): C6713/C6713B

• Eight 32 Bit Instructions/Cycle
• 32/64 Bit Data Word
• 200 and 300 MHz Clock Rate
• 5 Instruction Cycle Times
• 2400/1800 and 1600/1200 MIPS/MFLOPS
• Rich Peripheral Set, Optimized for Audio
• Highly Optimized C/C++ Compiler

Advanced Very Long Instruction Word (VLIW) 320C67x DSP Core

• Eight Independent Functional Units:
  • Two ALUs (Fixed Point)
  • Four ALUs (Floating Point and Fixed Point)
  • Two Multipliers (Floating Point and Fixed Point)
• Load Store Architecture With 32 32-Bit General Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional

Instruction Set Features

• Native Instructions for IEEE 754
• Byte Addressable (8/16/32 Bit Data)
• 8 Bit Overflow Protection
• Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization

L1/L2 Memory Architecture

• 4K Byte L1P Program Cache (Direct-Mapped)
• 4K Byte L1D Data Cache (2-Way)
• 256K Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM,
  and 192K Byte Additional L2 Mapped RAM

Device Configuration

• Boot Mode: HPI, 8/16/32 Bit ROM Boot
• Endianness: Little Endian, Big Endian

32 Bit External Memory Interface (EMIF)

• Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM
• 512M Byte Total Addressable External Memory Space

Enhanced Direct Memory Access (EDMA) Controller (16 Independent Channels)

16 Bit Host Port Interface (HPI)

Two Multichannel Audio Serial Ports (McASPs)

• Two Independent Clock Zones Each (One TX and One RX)
• Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones
• Wide Variety of I²S™ and Similar Bit Stream Formats
• Integrated Digital Audio Interface Transmitter (DIT)
• Extensive Error Checking and Recovery

Two Inter-Integrated Circuit Bus (I²C™ Bus)
Multi-Master and Slave Interfaces

Two Multichannel Buffered Serial Ports:

• Serial Peripheral Interface (SPI)
• High Speed TDM Interface
• AC97 Interface

Two 32 Bit General Purpose Timers

Dedicated GPIO Module With 16 Pins (External Interrupt Capable)

Flexible Phase Locked Loop (PLL) Based Clock Generator Module

IEEE-1149.1 (JTAG) ⁽¹⁾ Boundary-Scan Compatible

272 Ball, Ball Grid Array Package (GDP)

0.13 µm/6 Level Copper Metal Process

• CMOS Technology

3.3 V I/Os, 1.26 V Internal

SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS

• Controlled Baseline
• One Assembly/Test Site
• One Fabrication Site
• Available in Military (–55°C/125°C) Temperature Range⁽²⁾
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability