DSP Fixed-Point 32-Bit 4752MIPS 361-Pin NFBGA

The TMS320DM6441 (also referenced as DM6441) leverages TI"s DaVincitechnology to meet the networked media encode and decode application processingneeds of next-generation embedded devices. The DM6441 enables OEMs and ODMs to quickly bring to market devices featuringrobust operating systems support, rich user interfaces, high processingperformance, and long battery life through the maximum flexibility of a fullyintegrated mixed processor solution. The dual-core architecture of the DM6441 provides benefits of both DSP andReduced Instruction Set Computer (RISC) technologies, incorporating ahigh-performance TMS320C64x+ DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bitinstructions and processes 32-bit, 16-bit, or 8-bit data. The core usespipelining so that all parts of the processor and memory system can operatecontinuously. The ARM core incorporates: A coprocessor 15 (CP15) and protection module Data and program memory management units (MMUs) with table look-asidebuffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-wayassociative with virtual index virtual tag (VIVT). The TMS320C64x+ DSPs are the highest-performance fixed-point DSP generationin the TMS320C6000 DSP platform. It is based on an enhanced version of thesecond-generation high-performance, advanced very-long-instruction-word (VLIW)architecture developed by Texas Instruments (TI), making these DSP cores anexcellent choice for digital media applications. The C64x is a code-compatiblemember of the C6000 DSP platform. The TMS320C64x+ DSP is an enhancement of theC64x+ DSP with added functionality and an expanded instruction set. Any reference to the C64x DSP or C64x CPU also applies, unless otherwisenoted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4104 million instructions per second (MIPS) at aclock rate of 513 MHz, the C64x+ core offers solutions to high-performance DSPprogramming challenges. The DSP core possesses the operational flexibility ofhigh-speed controllers and the numerical capability of array processors. TheC64x+ DSP core processor has 64 general-purpose registers of 32-bit word lengthand eight highly independent functional units&151;two multipliers for a32-bit result and six arithmetic logic units (ALUs). The eight functional unitsinclude instructions to accelerate the performance in video and imagingapplications. The DSP core can produce four 16-bit multiply-accumulates (MACs)per cycle for a total of 2052 million MACs per second (MMACS), or eight 8-bitMACs per cycle for a total of 4104 MMACS. For more details on the C64x+ DSP, seethe TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide(literature number SPRU732). The DM6441 also has application-specific hardware logic, on-chip memory, andadditional on-chip peripherals similar to the other C6000 DSP platform devices.The DM6441 core uses a two-level cache-based architecture. The Level 1 programcache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D)is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)consists of an 512K-bit memory space that is shared between program and dataspace. L2 memory can be configured as mapped memory, cache, or combinations ofthe two.

Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation.

High-Performance Digital Media SoC

• C64x+™ DSP Clock Rate
  • 405-MHz (Max) at 1.05 V or 513-MHz (Max) at 1.2 V
• ARM926EJ-S™ Clock Rate
  • 202.5-MHz (Max) at 1.05 V or 256-MHz (Max) at 1.2 V
• Eight 32-Bit C64x+ Instructions/Cycle
• 4752 C64x+ MIPS
• Fully Software-Compatible With C64x &153; ARM9™

Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core

• Eight Highly Independent Functional Units
  • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
• Load-Store Architecture With Non-Aligned Support
• 64 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional
• Additional C64x+™ Enhancements
  • Protected Mode Operation
  • Exceptions Support for Error Detection and Program Redirection
  • Hardware Support for Modulo Loop Operation

C64x+ Instruction Set Features

• Byte-Addressable (8-/16-/32-/64-Bit Data)
• 8-Bit Overflow Protection
• Bit-Field Extract, Set, Clear
• Normalization, Saturation, Bit-Counting
• Compact 16-Bit Instructions
• Additional Instructions to Support Complex Multiplies

C64x+ L1/L2 Memory Architecture

• 32K-Byte L1P Program RAM/Cache (Direct Mapped)
• 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
• 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/CacheAllocation)

ARM926EJ-S Core

• Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
• DSP Instruction Extensions and Single Cycle MAC
• ARM® Jazelle® Technology
• Embedded ICE-RT™ Logic for Real-Time Debug

ARM9 Memory Architecture

• 16K-Byte Instruction Cache
• 8K-Byte Data Cache
• 16K-Byte RAM
• 8K-Byte ROM

Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug

Endianness: Little Endian for ARM and DSP

Video Imaging Co-Processor (VICP)

Video Processing Subsystem

• Front End Provides:
  • CCD and CMOS Imager Interface
  • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  • Preview Engine for Real-Time Image Processing
  • Glueless Interface to Common Video Decoders
  • Histogram Module
  • Auto-Exposure, Auto-White Balance, and Auto-Focus Module
  • Resize Engine
    • Resize Images From 1/4× to 4×
    • Separate Horizontal/Vertical Control
• Back End Provides:
  • Hardware On-Screen Display (OSD)
  • Four 54-MHz DACs for a Combination of
    • Composite NTSC/PAL Video
    • Luma/Chroma Separate Video (S-video)
    • Component (YPbPr or RGB) Video (Progressive)
  • Digital Output
    • 8-/16-bit YUV or up to 24-Bit RGB
    • HD Resolution