Active Programmable Delay Line 1-IN 0.01ns ABS 12.4ns MAX 32-Pin LQFP T/R

The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from V to V to fine tune the output delay from 0 to 60 ps.

• Maximum Frequency > 1.2 GHz Typical
• PECL Mode Operating Range: V_CC = 3.0 V to 3.6 V with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V with V_EE = -3.0 V to -3.6 V
• Open Input Default State
• Safety Clamp on Inputs
• A Logic High on the ENbar Pin Will Force Q to Logic Low
• D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
• V_BB Output Reference Voltage
• Pb-Free Packages are Available