SRAM Chip Sync Single 1.8V 72M-Bit 4M x 18 0.45ns 165-Pin FBGA

The GS8672T20BE -II+ ECCRAMs are built in compliance with the -II+ SRAM pin out standard for Common I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8672T20BE SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

• 2.5 Clock Latency
• On-Chip ECC with virtually zero SER
• Simultaneous Read and Write ™ Interface
• Common I/O bus
• JEDEC-standard package
• Double Data Rate interface
• Byte Write capability
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (DQ), Byte Write (BW), and Clock (K, K) outputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with 36Mb and 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available