SRAM Chip Sync Single 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin FBGA

The CY7C1318JV18, and CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a one bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. For CY7C1318JV18 and CY7C1320JV18, the burst counter takes in the least significant bit of the external address and bursts two 18 bit words (in the case of CY7C1318JV18) of two 36 bit words (in the case of CY7C1320JV18) sequentially into or out of the device.

• 18 Mbit Density (1M x 18, 512K x 36)
• 300 MHz Clock for High Bandwidth
• Two word Burst for reducing Address Bus Frequency
• Double Data Rate (DDR) Interfaces (data transferred at 600 MHz) at 300 MHz
• Two Input Clocks (K and K) for Precise DDR Timing
  • SRAM uses rising edges only
• Two Input Clocks for Output Data (C and C) to Minimize Clock Skew and Flight Time mismatches
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed systems
• Synchronous Internally self timed Writes
• DDR II Operates with 1.5 Cycle Read Latency when the DLL is enabled
• Operates similar to a DDR I Device with 1 Cycle Read Latency in DLL Off Mode
• 1.8V Core Power Supply with HSTL Inputs and Outputs
• Variable drive HSTL Output Buffers
• Expanded HSTL Output Voltage (1.4V-VDD)
• Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)
• Offered in both Pb-free and non Pb-free packages
• JTAG 1149.1 Compatible Test Access Port
• Delay Lock Loop (DLL) for Accurate Data Placement