SRAM Chip Sync Dual 3.3V 576K-Bit 16K x 36 18ns/6ns 144-Pin TQFP

The CY7C09569V is high-speed 3.3 V synchronous CMOS 16 K and 32 K × 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time.

• True dual-ported memory cells which allow simultaneous access of the same memory location
• Two flow-through/pipelined devices
  • 16 K × 36 organization (CY7C09569V)
• 0.25-micron CMOS for optimum speed/power
• Three modes
  • Flow-through
  • Pipelined
  • Burst
• Bus-matching capabilities on right port (× 36 to × 18 or × 9)
• Byte-select capabilities on left port
• 100-MHz pipelined operation
• High-speed clock to data access 5/6 ns
• 3.3 V low operating power
  • Active = 250 mA (typical)
  • Standby = 10 µA (typical)
• Fully synchronous interface for ease of use
• Burst counters increment addresses internally
  • Shorten cycle times
  • Minimize bus noise
  • Supported in flow-through and pipelined modes
• Counter address read back via I/O lines
• Single chip enable
• Automatic power-down
• Commercial and industrial temperature ranges