SRAM Chip Sync Dual 2.5V/3.3V 18M-Bit 1M x 18 4.2ns/2.5ns 100-Pin TQFP

The GS816018D is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

• Military Temperature Range
• FT pin for user-configurable flow through or pipeline operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• RoHS-compliant 100-lead TQFP package
• 1MB product Family
• 13 mm x 15 mm, 165 FPBGA
• Default to SCD x18 Interleaved Pipeline mode