SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin FBGA

The CY7C1424V18 is 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate ports to access the memory array. The Read port has dedicated Data outputs and the Write port has dedicated Data inputs to completely eliminate the need to “turn around’ the data bus required with common I/O devices. Access to each port is accomplished using a common address bus. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 36-bit words in the case of CY7C1424AV18, that burst sequentially into or out of the device. Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR-II SIO SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K/K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clock. Writes are conducted with on-chip synchronous self-timed write circuitry.

• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
• 300-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V-VDD)
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both lead-free and non lead-free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement