SRAM Chip Async Single 5V 512K-Bit 32K x 16 12ns 44-Pin TSOP-II

The CY7C1020B is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable and Write Enable inputs LOW. If Byte Low Enable is LOW, then data from I/O pins, is written into the location specified on the address pins. If Byte High Enable is LOW, then data from I/O pins is written into the location specified on the address pins. Reading from the device is accomplished by taking Chip Enable and Output Enable LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins are placed in a high-impedance state when the device is deselected, the outputs are disabled. The CY7C1020B is available in standard 44-pin TSOP Type II and 400-mil-wide SOJ packages.

• High speed
  • tAA = 12, 15 ns
• CMOS for optimum speed/power
• Low active power
  • 825 mW (max.)
• Low CMOS standby power (L version only)
  • 2.75 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ