SRAM Chip Async Single 5V 4M-Bit 256K x 16 10ns 44-Pin TSOP-II

CY7C1041GN is high-performance CMOS fast static RAM Organized as 256K words by 16-bits. Data writes are performed by asserting the Chip Enable (CE\) and Write Enable (WE\) inputs LOW, while providing the data on I/O0 through I/O15 and address on A0 through A17 pins. The Byte High Enable (BHE\) and Byte Low Enable (BLE\) inputs control write operations to the upper and lower bytes of the specified memory location. BHE\ controls I/O8 through I/O15 and BLE\ controls I/O0 through I/O7. Data reads are performed by asserting the Chip Enable (CE\) and Output Enable (OE\) inputs LOW and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). Byte accesses can be performed by asserting the required byte enable signal (BHE\ or BLE\) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a high-impedance state during the following events: The device is deselected (CE\ HIGH), The control signals (OE\, BLE\, BHE\) are de-asserted.

• High speed: tAA = 10 ns / 15 ns
• Low active and standby currents
  • Active current: Icc = 38-mA typical
  • Standby current: Isb2 = 6-mA typical
• Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V to 5.5 V
• 1.0-V data retention
• TTL-compatible inputs and outputs
• Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA packages