SRAM Chip Async Single 5V 1M-Bit 128K x 8 55ns 32-Pin SOIC

The CY621282BN is a high-performance CMOS static RAM organized as 128K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable, an active HIGH Chip Enable, and active LOW Output Enable. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking Chip Enable One and Write Enable inputs LOW and Chip Enable Two input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One and Output Enable LOW while forcing Write Enable and Chip Enable Two HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected, the outputs are disabled, or during a write operation.

• Temperature Ranges
  • Automotive-E: -40 °C to 125 °C
• 4.5 V to 5.5 V operation
• Complementary metal oxide semiconductor (CMOS) for optimum speed/power
• Low active power 137.5 mW (max.) (25 mA)
• Low standby power 137.5 µW (max.) (25 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE/ and OE1/, CE2, and options
• Available in Pb-free 32-pin (450 mil-wide) small outline integrated circuit (SOIC) package