SRAM Chip Async Single 3V 4M-Bit 512K x 8 70ns 32-Pin TSOP-II T/R

The CY62148V is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable, an active LOW output enable, and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 99% when deselected. Writing to the device is accomplished by taking chip enable and write enable inputs LOW. Data on the eight I/O pins is then written into the location specified on the address pins. Reading from the device is accomplished by taking chip enable and output enable LOW while forcing write enable HIGH for read. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins are placed in a high-impedance state when the device is deselected, the outputs are disabled, or during a write operation. The CY62148V is available in a standard 32 pin 450-mil-wide body width SOIC and 32 pin TSOPII packages.

• 2.7V-3.6V operation
• CMOS for optimum speed/power
• Low active power
  • 180 mW (max.)
• Low standby power (Commercial LL version)
  • 54 µW (max.)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE/ and OE/ and options