SRAM Chip Async Dual 1.8V 128K-Bit 16K x 8 55ns 100-Pin TQFP

The CYDC128B08 are low-power CMOS 4K, 8K,16K x 16, and 8/16K x 8 dual-port static RAMs. Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.Each port has independent control pins: Chip Enable, Read or Write Enable, and Output Enable. Two flags are provided on each port. BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a Chip Enable pin.

• True dual-ported memory cells that allow simultaneous access of the same memory location
• Synchronous pipelined operation
• Organization of 1 Mbit, 2 Mbits, 4 Mbits and 9 Mbits devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
  • Active as low as 225 mA (typ)
  • Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 256-ball FBGA (1 mm pitch)
• Counter wrap-around control
  • Internal mask register controls counter wrap-around
  • Counter-interrupt flags to indicate wrap-around
  • Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth expansion
• Seamless migration to next-generation dual-port family