Combo Mem 2Mx16/4Mx8 Flash + 1Mx16 PSRAM 3.3V

The SST34HF32A4 ComboMemory integrates either a 2M x16 or 4M x8 CMOS flash memory bank with 1024K x16 CMOS pseudo SRAM (PSRAM) memory bank in a multichip package (MCP). This device is fabricated using SST proprietary, high-performance CMOS SuperFlash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF32A4 is ideal for applications such as cellular phones, GPS devices, PDAs, and other portable electronic devices in a low power and small form factor system. The SST34HF32A4 features dual flash memory bank architecture allowing for concurrent operations between the two flash memory banks and the PSRAM. The device can read data from either bank while an Erase or Program operation is in progress in the opposite bank. The two flash memory banks are partitioned into 8 Mbit and 24 Mbit with top sector protection options for storing boot code, program code, configuration/parameter data and user data. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF32A4 offers a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high-performance Program operations, the flash memory banks provide a typical Word-Program time of 7 µsec. To protect against inadvertent flash write, the SST34HF32A4 contains on-chip hardware and software data protection schemes. Flash Organization: 2M x16 or 4M x8 Dual-Bank Architecture for Concurrent Read/Write Operation 32 Mbit Top Sector Protection 32 Mbit: 8 Mbit + 24Mbit PSRAM Organization: 16 Mbit: 1024K x16 Single 2.7-3.3V Read and Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than 100 years Data Retention Low Power Consumption: Active Current: 25 mA (typical) Standby Current: 70 µA (typical) Hardware Sector Protection Hardware Reset Pin (RST#) Resets the internal state machine to reading data array Byte Selection for Flash (CIOF pin) Selects 8-bit or 16-bit mode (56-ball package only) Sector-Erase Capability Uniform 2 KWord sectors Flash Chip-Erase Capability Block-Erase Capability – Uniform 32 KWord blocks Erase-Suspend / Erase-Resume Capabilities Read Access Time Flash: 70 ns PSRAM: 70 ns Security ID Feature SST: 128 bits User: 256 Bytes Latched Address and Data Fast Erase and Program Automatic Write Timing Internal VPP Generation End-of-Write Detection Toggle Bit Data# Polling Ready/Busy# pin CMOS I/O Compatibility JEDEC Standard Command Set Packages Available 56-ball LFBGA (8mm x 10mm) 62-ball LFBGA (8mm x 10mm) All non-Pb (lead-free) devices are RoHS compliant