SRAM Chip Sync Quad 3.3V 1.125M-Bit 64K x 18 5ns 272-Pin BGA T/R

The Quadport Datapath Switching Element (DSE) family offers four ports that may be clocked at independent frequencies from one another. Each port can read or write up to 133 MHz[], giving the device up to 10 Gb/s of data throughput. The device is 1-Mb (64K × 18) in density. Simultaneous reads are allowed for accesses to the same address location; however, simultaneous reading and writing to the same address is not allowed. Any port can write to a certain location while other ports are reading that location simultaneously, if the timing spec for port to port delay is met. The result of writing to the same location by more than one port at the same time is undefined. Data is registered for decreased cycle time. Clock to data valid tCD2 = 4.2 ns. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address the counter will self-increment the address internally (more details to follow). The internal write pulse width is independent of the duration of the R/W input signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on0 or LOW on 1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle is required with chip enables asserted to reactivate the outputs.

• QuadPort™ datapath switching element (DSE) family allows four independent ports of access for data path management and switching
• High-bandwidth data throughput up to 10 Gb/s
• 133-MHz port speed x 18-bit-wide interface × 4 ports
• High-speed clock to data access 4.2 ns (maximum)
• Synchronous pipelined device
  • 1 Mb (64K × 18) switch array
• 0.25-micron CMOS for optimum speed/power
• IEEE 1149.1 JTAG boundary scan
• Width and depth expansion capabilities
• BIST (Built-In Self-Test) controller
• Dual Chip Enables on all ports for easy depth expansion
• Separate upper-byte and lower-byte controls on all ports
• Simple array partitioning
  • Internal mask register controls counter wrap-around
  • Counter-Interrupt flags to indicate wrap-around
  • Counter and mask registers readback on address
• 272-ball BGA package (27-mm × 27-mm × 1.27-mm ball pitch)
• Commercial and industrial temperature ranges
• 3.3 V low operating power
  • Active = 750 mA (maximum)
  • Standby = 15 mA (maximum)