SRAM Chip Sync Dual 3.3V 4M-Bit 256K x 18 4ns 100-Pin TQFP

The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.

• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Byte Write capability
• 256K x 18 common I/O architecture
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (OE)
• Available in lead-free 100-Pin TQFP package
• Burst Capability linear or interleaved burst order
• ZZ” Sleep Mode Option and Stop Clock option