SRAM Chip Sync Dual 2.5V 9M-Bit 512K x 18 2.5ns 165-Pin FBGA Tray

The CY7C1302DV25 is a 2.5 V Synchronous Pipelined SRAM equipped with QDR architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock.

• Separate independent Read and Write data ports
  • Supports concurrent transactions
• 167-MHz clock for high bandwidth
  • 2.5 ns Clock-to-Valid access time
• 2-word burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz
• Two input clocks for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data to minimize clock-skew and flight-time mismatches.
• Single multiplexed address input bus latches address inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5 V core power supply with HSTL Inputs and Outputs
• Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4 V-1.9 V)
• JTAG Interface