Rohstoff-Handelsplattform

SRAM Chip Sync Dual 1.8V 72M-Bit 4M x 18 0.5ns 165-Pin FBGA Tray

The GSQ8662Q18E is built in compliance with the Sigma Quad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GSQ8662Q18E Sigma Quad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. The GSQ8662Q18E Sigma Quad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each internal read and write operation in a Sigma Quad-II B2 RAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a Sigma Quad-II B2 RAM is always one address pin less than the advertised index depth (e.g., the 8M x 8 has an 4M addressable index).
  • Simultaneous Read and Write SigmaQuad™ Interface
  • JEDEC-standard pinout and package
  • Dual Double Data Rate interface
  • Byte Write controls sampled at data-in time
  • Burst of 2 Read and Write
  • 1.8 V +100/–100 mV core power supply
  • 1.5 V or 1.8 V HSTL Interface
  • Pipelined read operation
  • Fully coherent read and write pipelines
  • ZQ pin for programmable output drive strength
  • IEEE 1149.1 JTAG-compliant Boundary Scan
  • Pin-compatible with present 9Mb, 18Mb, and 36Mb and future 144Mb devices
  • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
  • RoHS-compliant 165-bump BGA package available

Spezifikationen

Brand GSI Technology
Datasheet PDF
Timing Type Synchronous
Number Of Words 4 MWords
Density 72 Mbit
Operating temperature -40 to 85 °C
Pin Count 165
Number Of Ports 2
Mounting Surface Mount
Address B 21 Bit
Number Of 18 Bit
Number Of 18 Bit
Maximum O 775 mA
Product description 17 x 15 x 1.04 mm
Maximum R 0.5 ns
Supplier FBGA
Typical O 1.8000 V
ECCN 3A991.B.2.B
Schedule B 8542320040
HTSN 8542320041
Screening Level Industrial
Minimum O 1.7 V
Maximum O 1.9 V
Maximum C 167 MHz
Data Rate DDR
Architecture Pipelined
Lead Finish Tin/Lead
Msl Level 3
SKU: GS8662Q18E-167I