SRAM Chip Sync Dual 1.8V 72M-Bit 4M x 18 0.45ns 165-Pin FBGA Bulk

The GS8672T19B ECCRAMs are built in compliance with the -II+ SRAM pin out standard for Common I/O synchronous ECCRAMs. They are 75,497,472-bit (72Mb) ECCRAMs. The GS8672T19/37BE Sigma CIO ECCRAMs are just one element in a family of low power, low voltage HSTL I/O ECCRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

• On-Chip ECC with virtually zero SER
• 2.0 Clock Latency
• Simultaneous Read and Write ™ Interface
• Common I/O bus
• JEDEC-standard pin out and package
• Double Data Rate interface
• Byte Write Capability
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with 18Mb, 36Mb and 144Mb devices
• 14 mm x 22 mm, 119 BGA
• RoHS-compliant 165-bump BGA package available
• 64MB or 72MB product family