SRAM Chip Sync Dual 1.8V 2M-Bit 64K x 36 3.3ns 256-Pin FBGA Tray

The FullFlex dual port SRAM families consist of 2-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode.

• True dual port memory enables simultaneous access the shared array from each port
• Synchronous pipelined operation with single data rate (SDR) operation on each port
  • SDR interface at 200 MHz
  • Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)
• Selectable pipelined or flow-through mode
• 1.5 V or 1.8 V core power supply
• Commercial and Industrial temperature
• IEEE 1149.1 JTAG boundary scan
• Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36 and × 18) packages
• FullFlex36 family
  • 2-Mbit: 64 K × 36 (CYD02S36V18)
• Built in deterministic access control to manage address collisions
  • Deterministic flag output upon collision detection
  • Collision detection on back-to-back clock cycles
  • First busy address readback
• Advanced features for improved high speed data transfer and flexibility
  • Variable impedance matching (VIM)
  • Echo clocks
  • Selectable LVTTL (3.3 V), Extended HSTL (1.4 V to 1.9 V), 1.8 V LVCMOS, or 2.5 V LVCMOS IO on each port
  • Burst counters for sequential memory access
  • Mailbox with interrupt flags for message passing
  • Dual chip enables for easy depth expansion