SRAM Chip Async Single 5V 4M-Bit 512K x 8 70ns 32-Pin TSOP

The AS5C4009 is organized as 524,288 x 8 SRAM utilizing a special ultra low power design process. The pinout adheres to the JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32 pin version allows for easy upgrades from the 1 meg SRAM design. These features can place the outputs in High-Z for additional flexibility in system design.This devices operates from a single +5V power supply and all inputs and outputs are fully TTL-compatible.Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode when disabled, by lowering VCC to 2V and maintaining CE\ = 2V. This allows system designers to meet ultra low standby power requirements.

• Ultra Low Power with 2V Data Retention (0.2mW MAX worst case Power-down standby)
• Fully Static, No Clocks
• Single +5V ±10% power supply
• Easy memory expansion with CE\ and OE\ options
• All inputs and outputs are TTL-compatible
• Three state outputs
• Operating temperature range:
  • Ceramic -55°C to +125°C & -40°C to +85°C Plastic -40°C to +85°C